1. Field of the Invention
The present invention relates generally to field effect transistors (FET's) formed as complimentary metal oxide semiconductor (CMOS) structures and, more particularly, to new and improved MOSFET devices having vertically oriented channel structures capable of fully depleted operation at short channel lengths, thereby providing a device for robust I/O applications. Specifically, the present invention relates to an improved MOSFET device and method of fabrication that provides high performance analog and mixed-signal solutions useful in a wide variety of applications.
2. Description of the Prior Art
The progression of CMOS device scaling, that is planer MOSFET, has seen a continuous shrinking of transistor dimensions in both the vertical and the horizontal dimensions resulting in an approximate doubling of the number of transistors per unit area every 18 months or so. From the economics perspective, this scaling progression has resulted in CMOS becoming the preeminent technology for packing system functions on a transistor chip. The desire to shrink gate channel lengths and hence area, as width-to-length ratios remain roughly constant, requires the simultaneous vertical scaling of both the gate oxide and the source/drain junctions. This creates the requirement that the power supply (Vdd) also scale, as indicated above. The power supply voltage must scale so as to maintain gate oxide integrity (breakdown/wear-out due to voltage stress), to provide adequate junction breakdown margin, and to minimize device lifetime reduction due to hot carrier injection.
While CMOS scaling has enabled the circuit and system designer to pack a tremendous amount of functionality onto a silicon die, it has simultaneously created a number of significant problems as far as the chip's ability to interface with the outside world. This is particularly true in the area of analog/digital mixed-signal chips, and in particular for communication and power management applications which may be used or exist in a less-controlled signaling environment than found in all-digital systems. Some examples of the efforts to overcome this are illustrated in U.S. Pat. Nos. 4,393,391, 5,675,164, 5,801,417, 5,932,911, 6,111,296, 6,118,161, 6,207,511, 6,396,108 and U.S. Pat. No. 6,413,802.
As a result of the above, the continuing drive to utilize semiconductor chip area while maintaining I/O compatibility has resulted in the evolution of baseline CMOS ASIC/SOC process technologies that now have two gate oxides to account for the need to operate efficiently at two, and sometimes three, power supply levels. Having begun at roughly the 0.25 um node, this is currently the approach taken by certain mainstream ASIC/ASSP semiconductor producers or foundries. These technology offerings generally consist of a baseline process flow that has a fully scaled and optimized thin oxide core device to the extent that the current process manufacturing technology allows, and a thick oxide device which is essentially the core device from the previous technology generation. Unfortunately, in such technology evolution, the thick oxide I/O device has become somewhat of a “forgotten stepchild”, as only the thin-oxide core devices can truly take advantage of the shrinking feature sizes that are enabled by state-of-the-art photolithography. More importantly, as the thick oxide device is a “leftover” from the previous technology node, it typically under-performs the thin-oxide core device in terms of speed/bandwidth (ft).
The impact of this trend is particularly acute in the area of all-CMOS analog and mixed analog/digital signal chips. These chips derive their advantage from the ability to integrate complex digital core functions, such as DSP, with analog signal processing functions, such as analog-to-digital or digital-to-analog converters. While this reliability-driven voltage trend results in lower power consumption for digital functions, the effect is not necessarily the same in the analog case. In fact, it has been shown that in an analog-to-digital converter application with a fixed dynamic range requirement, power consumption can actually increase with decreasing power supply.
More problematic from the standpoint of device reliability and survivability is the significantly harsher EMI (electromagnetic induction)/ESD (electrostatic discharge) environment seen by I/O devices used in mixed-signal communications applications. To further illustrate this problem, some typical mixed-signal I/O and communications interfaces include system backplane, chip-to-chip and cell phone (RF). In many such electronic systems, the power supply voltage is specified within a 3-sigma tolerance of ±10%. However, in a data transmission or communication situation, there is the additional problem of signal reflections due to improperly terminated transmission lines.
In the first two mixed-signal examples, that is system backplane and chip-to-chip, a termination problem could chronically arise due to manufacturing tolerances, or as the result of devices connecting and disconnecting from the bus, or perhaps as a “hot swap” situation. Another common example of a harsh ESD/EOS environment is that of the cellular phone. The power amp of the transmitter must be able to tolerate the high VSWR conditions that can occur under large output load mismatch conditions. This can happen if the cell-phone antenna is touched or pulled-off during the transmission of a call.
Another important factor for consideration when discussing I/O robustness in bulk CMOS technologies is that of latch-up, where a low impedance path is created between the power supply rail and the ground rail as a result of the interaction of parasitic p-n-p and n-p-n bipolar transistors. One of the known causes of latch-up is an ESD event that results in the injection of minority carriers from the clamping device in the protection circuit into either the substrate bulk or the well. In a harsh I/O environment, transmission line reflections may also trigger the ESD protect device, thus increasing the probability that a latch-up condition can occur.
At present, BiCMOS (bipolar-CMOS combination) technologies, and particularly SiGe bipolar, offer a solution to some of the problems discussed above. However, a number of difficulties persist including, in particular, power consumption, cost and scalability. Bipolar devices consume significantly more power than CMOS devices, which increases package cost and at some point renders them unsuitable as a system solution, in particular for portable devices. From the standpoint of scaling, bipolar technologies have hit an apparent limit in terms of increasing performance for a given density and power consumption. The integration of CMOS and bipolar devices (BiCMOS) reduces the power consumption problem but leads to a second difficulty, i.e. cost. High performance technologies, such as SiGe BiCMOS cost upwards of 25% or more than CMOS devices at the same feature sizes. Finally, bipolar devices by nature, like the thick oxide CMOS I/O devices discussed earlier, cannot take full advantage of decreasing feature sizes which result from advances in wafer patterning technology (photolithography).
Clearly, the trends and problems discussed above may soon create a situation where it is no longer desirable to integrate a significant amount of analog functionality into a single-chip mixed-signal system solution, thus eliminating one of the traditional paths to reduce cost and power consumption in electronic systems. Accordingly, there is a need for a new type of silicon technology platform that takes advantage of the low power and economic advantages of CMOS in addition to enhancing the I/O function through decreasing feature sizes. There have been numerous attempts to develop such devices which overcome the aforementioned problems. Some specific examples of these efforts are illustrated in U.S. Pat. Nos. 6,111,296, 6,127,702, 6,198,141, 6,355,532 and E.P Patent No. 1,091,413. However, these problems still persist. Therefore, there remains a need in the art for such a device, and the present invention addresses and solves these particular problems in the art.